Streaming video, cloud services and mobile data are driving the continued growth of global network traffic. To support this growth, network systems must provide faster line rates and the ability to process millions of packets per second. In a network system, the order in which packets arrive is random, and the processing of each packet requires several storage actions. Packet traffic requires hundreds of millions of memories per second to find paths or complete statistics in the forwarding table.
The packet rate is proportional to the random access rate. Today's network devices require high random access rate (RTR) performance and high bandwidth to keep up with today's rapidly growing network traffic. Among them, RTR is the number of times that the memory can perform completely random storage (read or write), that is, the random storage rate. This metric is independent of the number of bits processed during the access process. RTR is measured in millions of times per second (MT/s).
Today's high-performance DRAMs can handle less than the rate of random traffic that high-performance network systems need to handle. The QDR-IV SRAM is designed to provide best-in-class RTR performance to meet demanding network functional requirements. Figure 1 quantifies the advantages of QDR-IV in terms of RTR performance over other types of memory. Even with the highest performance memory, QDR-IV can provide twice the RTR performance of the latter, so it is those that need to perform demanding operations - such as updating statistics, tracking data flow status, scheduling data packets, Ideal for high performance network systems for table lookups.
In the first part of this series, we will explore two types of QDR-IV memory, clock, read/write operations, and grouping operations.
Figure 1. QDR-IV performance comparison
Different types of QDR-IV: XP and HP
There are two types of QDR-IV. HP works at lower frequencies and does not use grouping operations. For the highest performance applications, XP can use a grouping scheme and work at higher frequencies.
The read and write latency of QDR-IV is determined by the operating speed. Table 1 defines the operating modes and the frequencies supported by each mode.
Table 1. Working mode
The QDR-IV SRAM has two ports, Port A and Port B. Since these two ports can be accessed independently, any combination of read/write access to the memory array can achieve the maximum random data transfer rate. In QDR-IV, a double data rate universal address bus (A) is required for each port access. The address of Port A is latched on the rising edge of the input clock (CK), while the address of Port B is latched on the falling edge of the input clock (CK) or on the rising edge of CK#. The control signals (LDA#, LDB#, RWA#, and RWB#) operate at a single data rate (SDR) and are used to determine whether to perform a read or write operation. Both data ports (DQA and DQB) are equipped with double data rate (DDR) interfaces. The device has a 2-word burst architecture. The data bus bandwidth of the device is &TImes; 18 or &TImes; 36.
The QDR-IV SRAM includes two ports designated as Port A and Port B. Because access to the two ports is independent, the random transaction rate is maximized for any combination of read/write accesses to the memory array. Access to each port is through a common address bus (A) running at double data rate (ie, the two edges of the clock). The address of port A is latched on the rising edge of the input clock (CK), and the address of port B is latched on the falling edge of CK or the rising edge of CK#. The control signals (LDA#, LDB#, RWA#, and RWB#) operate at a single data rate (SDR), which determines whether to perform a read or write operation. Both data ports (DQA and DQB) are equipped with double data rate (DDR) interfaces. The device uses a 2-word burst architecture. It provides &TImes;18 and &TImes;36 data bus width.
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