Today's electronic products such as computers, PADs, mobile phones, and communication system equipment are processing faster and faster, computing power is getting stronger, and the design of power supplies is becoming more and more complicated. After entering the 21st century, the chip manufacturing process has been gradually upgraded from 0.18um to 95nm, 65nm, 45nm. The integration of transistors is higher, the frequency is higher, and the power supply voltage is lower, which brings more design and debugging of the product. Big challenge. In the 1990s, the chip's power supply was usually 5V and 3.3V, using CMOS or TTL levels. Now, many digital circuit chips have core voltages and IO levels of less than 3.3V, using the most commonly used memory chips as an example. The old SDR SDRAM supply voltage is 3.3V, DDR SDRAM is 2.5V, DDR2 is 1.8V, DDR3 is 1.5V, and the latest DDR4 is 1.2V, and its VREF is only 0.6V. The supply voltage of these circuits is getting smaller and smaller, and the requirements for power supply noise are more stringent. How to design a low-noise power supply and accurately measure its power supply noise is very important. This article will take the perspective of Power Integrity (PI). Briefly analyze the problems that may be encountered in the power supply noise test and the corresponding solutions. 
Power supply noise and PDN
In communication and computer products, whether it is CPU, GPU, FPGA, DDR3, there are thousands of transistors inside the chip. The circuits with different functions in the chip have different power sources, such as the power supply VCore of the core circuit, input and output buffer ( IO Buffer) power supply, internal clock or PLL power supply, etc. These power supplies come from the upper DC stabilized power supply module of the board.
Figure 1 below is a schematic diagram of a power distribution network (PDN) of a chip. The power supply loop of the chip starts from the voltage regulator module VRM (Voltage Regulator Module), passes through the power supply network on the PCB, and the ball pin of the chip. The chip's power ground network finally reaches the silicon on the IC.
When various functional circuits on the chip work at the same time, the regulated power supply module VRM cannot respond to the load in rapid response to the rapid change of current demand, and the power supply voltage on the chip falls, thereby generating power supply noise. In order to ensure the stability of the output voltage, it needs to be packaged. Use decoupling capacitors on the PCB and a reasonable power plane to ground plane pair. From the perspective of current power integrity analysis, the industry generally believes that hundreds of megahertz PI problems can be handled on the PCB. Higher frequency power integrity issues need to be addressed during chip and package design. the reason is:
l, in the board-level PI design, it needs to be decoupled with a ceramic capacitor with a small capacitance and a small equivalent series inductance (ESL), such as a 0.1uf, 10nf capacitor in the 0603 package, but the PWR/GND wiring of the capacitor, The parasitic inductance brought by the via will increase the inductance, making the effective working frequency of the decoupling capacitor lower, and it is difficult to exceed several hundred MHz;
2, even if the board-level PI design can solve the PI problem of GHZ, the current of the power supply needs to be soldered to the ball of the PCB, the power/ground plane on the package, and the transistor that reaches the power has a long distance, and the effect is not great. . PI design puts decoupling above a few hundred MHz on the chip and package, and solves the decoupling problem of kHz – hundreds of MHz on the PCB.
Therefore, for board-level power supply noise testing, it is sufficient to use an oscilloscope with a bandwidth of 500M or more. Due to limited space, it is recommended to check the power integrity books for chip-level PI and board-level PI design, decoupling capacitor selection, etc.
Power Noise and Power Ripple
Power supply noise and ripple are two concepts that engineers often encounter and are confusing. Although they are very popular test items, there is no international association or standards organization that defines how to measure the power supply ripple and noise of DC power supplies. Figure 2 below shows the ripple and noise measured by the DC power output. The blue waveform is ripple and the red waveform is noise. The frequency of the ripple is the fundamental and harmonic of the switching frequency, and the frequency of the noise. The composition is higher than the ripple, which is caused by various factors such as the transient current generated by the switching of the high-speed I/O on the chip, the parasitic inductance of the power supply network, and the electromagnetic field radiation between the power plane and the ground plane. In recent years, the industry has gradually unified understanding that the source of the PDN (VRM) measures the ripple of the power supply output, while the sink side (chip) measures the power supply noise.
For the measurement of power supply ripple, after the industry's common oscilloscope limits the 20M bandwidth, the measured peak-to-peak value of the DC power supply output is the power supply ripple. It is recommended to measure the power supply ripple (bandwidth limited to 20MHz) in the following cases:
1, the power chip manufacturer's data sheet specified
2. When measuring AC-DC power, such as the output of ATX power supply
3, when measuring the output of the regulated power supply module
4. When measuring DC parameters, or when the on-board circuit operates at a low rate
From the perspective of PI, both linear LDO power supplies and switching power supplies can only provide stable power supply output in the low frequency band (kHz-MHz). The high frequency part of the power supply relies on PCB, package and fast charging in the chip. The discharge function is realized by the capacitance. When the on-chip chip operating rate is above tens of MHz, the power supply noise must be measured. The detection point should be as close as possible to the power supply pin of the chip to be tested.
Dongguan Pinji Electronic Technology Limited , https://www.iquaxusb4cable.com