MicroTCA is becoming an increasingly popular standard for embedded signal processing applications, especially high performance multiprocessor systems. These standards use advanced intermediate cards (AdvancedMC) that meet the needs of "carrier-grade" telecommunications equipment, finding ways to enter telecommunications applications, such as wireless baseband processing.
Wireless baseband processing is a high-demand application that requires an energy-efficient solution. Any system must also flexibly adapt to the requirements of multiple standards and adapt to the rapidly evolving standards of telecommunications. This article discusses various factors in the design process, including the choice of processors, interconnects, and software platforms.
For this flexible, high-performance application, the main choices for the processor are DSP and FPGA. In the past, DSPs were standard solutions, but FPGA vendors have improved their signal processing capabilities: many of today's applications benefit from a hybrid multiprocessor system that combines DSP and FPGA. A high-speed interconnect enables a subsystem to contain multiple DSPs (such as 3 or 4) and an FPGA, allowing designers to provide the right combination of performance to meet their system requirements.
As silicon vendors continue to increase their DSP and FPGA performance and add multiple cores to boost horsepower, embedded system designers must ensure that their data exchange architecture can keep up with this pace. Distributed applications require multiple levels of interconnection: between chips on a single board, between boards on a backplane, and between multiple racks.
A 20 MHz WiMAX baseband system with 2x2 Multiple Input Multiple Output (MIMO) requires an antenna data rate of approximately 1.5 Gbps. A typical base station supporting three sectors requires a joint interface rate of more than 4.5 Gbps, which can be supported by three independent radio head connections or one chain single connection. Interfaces based on open standards such as CPRI or OBSAI can be used for framing of data. When a MIMO system supporting a channel using a spread spectrum technique (such as CDMA) is used, all baseband processing blocks have data from all antennas.
In addition to raw performance, designers must also consider the cost of their chosen structure, including initial investment costs and operating costs. They should also seek standard interfaces to enable their designs to be reused across different platforms, both now and in the future, and to choose from a range of vendors that support standards.
Wireless baseband signal processing interconnectionFor high-performance signal processing applications, four structures are now generally considered: InfiniBand, PCI Express (PCIe), Ethernet, and Serial RapidIO (SRIO).
InfiniBand began to have strong support from Intel, but the company later stopped its development support and turned to support PCI Express. InfiniBand is designed as a switched fabric interconnect that can be used in local area networks and enterprise networks, but has recently been more oriented in storage applications. While technically it provides good features, especially in terms of management, it does not try to gain a foothold in embedded applications and there is no AdvancedMC specification for it.
PCIe is a serial version of PCI that provides a maximum data rate of 2.5 Gbps per lane. Typically, each AdvancedMC in MicroTCA is limited to four lanes. PCIe is particularly well-suited as a fast, low-cost peripheral, I/O connection to the host processor. It also has good support and a good number of adoptions, and some DSP and FPGA vendors use it as a native interface. However, in the case of more than a certain number of devices, PCIe does not have good scalability and is not suitable for multi-master processor environments, such as rack interconnects.
Therefore, PCIe is typically used for point-to-point connections associated with an independent data structure, as reflected in the recently announced SCOPE Alliance AdvancedMC Hardware Profile. In many cases, it is actually the choice of data structure between Ethernet (Gigabit and 10GigE) and SRIO.
Among many application types, Ethernet is a common choice. WiMax and LTE are IP technologies over Ethernet. The use of Ethernet for the transmission of base station backhaul networks is attracting attention. Gigabit Ethernet has been developed in different versions today and is widely used. 10GigE is supported in AdvancedMC through the XAUI standard. It has become ubiquitous since the early days of Ethernet in the WAN.
Gigabit Ethernet provides a point-to-point packet architecture with variable packet sizes. MicroTCA uses it as a basic structure to almost ensure the support of all AdvancedMCs in the rack on the control plane. There is currently no universal quality of service (QoS) standard for Gigabit Ethernet, and more and more routers and switches provide some QoS features that enable the basic structure to be used for low-bandwidth data plane transmission.
However, for large bandwidth data plane transmissions, the cost jump from Gigabit Ethernet to 10GigE is too large. Ethernet requires high CPU processing and packet protocol overhead, meaning that Ethernet is not an efficient implementation standard. Coupled with the high latency and jitter transmitted over Ethernet, designers may wish to look for other structures.
SERIAL RapidIODue to these issues, SRIO is gaining popularity in multiprocessor systems. It combines low cost, low power consumption, high flow and advanced features. Unlike PCI Express, SRIO can have multiple host processors and support multicast. It has lower protocol overhead than Ethernet, better flow control, and higher raw bandwidth utilization.
SRIO was originally developed for the interconnection of processors, which is suitable for both control plane and data plane transmission. It is a peer-to-peer packet architecture that supports any topology with low overhead. It allows the use of variable-size packet data packets and protocol data units (PDUs) of up to 256 bytes.
In addition to high traffic, SRIO is a highly efficient technology. It natively supports QoS, and Ethernet requires additional protocol layers and network interoperability. This gives SRIO a cost and power advantage over some data bandwidth.
Over the past few years, there has been a clear shift from PCI Express to SRIO in the DSP and signal processing markets. Crystal Cube ConsulTIng predicts that by 2011, SRIO-capable DSPs will account for 34% of the total DSP market, especially in wireless infrastructure applications. SRIO has been implemented on some of the main DSPs for baseband processing and can be obtained as a standalone FPGA IP core.
In wireless baseband processing applications such as CDMA and OFDMA, which support multiple-input multiple-output (MIMO) systems and use spread spectrum techniques, all RF antenna data must be sent to all baseband processing blocks. At this point, the key to achieving superior performance is the efficient low-latency interconnect that supports multicast, and SRIO is a good fit.
A blade-level subsystem solution may include both DSP and FPGA, choosing a combination of the two to suit the needs of a particular application. The SRIO architecture can be used for RF data distribution and for a low latency direct memory access (DMA) between devices, both on and off the card. Using SRIO for inter-card and in-card connections allows you to combine the various components.
In a wireless base station, SRIO can be used to transfer digital "chip rate" data from a user antenna to a baseband processing card in the system. Each baseband card has an SRIO interconnect and typically has a high performance DSP that supports SRIO. The data processed by the baseband card is then sent to the backhaul interface via SRIO.
WENZHOU TENGCAI ELECTRIC CO.,LTD , https://www.tengcaielectric.com