The basic characteristic of the phase-locked frequency synthesizer is that whenever the frequency-division ratio of the programmable frequency divider changes by 1, the output frequency increment is obtained as the reference frequency fr. In order to improve the frequency resolution, the reference frequency fr needs to be reduced, which is very detrimental to the performance such as conversion time. We imagine that if the programmable frequency divider can provide a fractional frequency division ratio, each time a certain decimal point is changed, then the frequency resolution can be improved without reducing the reference frequency. This is an ideal method, but unfortunately the digital divider itself cannot achieve fractional frequency division.
Fractional PLL synthesizer
Waveform of fractional PLL synthesizer circuit
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